A silicon carbide semiconductor has a large band gap as compared to a silicon (Si) semiconductor and therefore, has high dielectric breakdown electric field intensity. ON-resistance is resistance in a conductive state and is inversely proportional to the cube of the dielectric breakdown electric field intensity and therefore, for example, widely used silicon carbide semiconductors called a 4H type (four-layer cycle hexagonal crystals: 4H—SiC) can suppress the ON-resistance to a few hundredth as compared to silicon semiconductors.
Therefore, also because of large thermal conductivity characteristics facilitating heat radiation, silicon carbide semiconductors are expected as a next-generation, low-loss, power semiconductor device. For example, a silicon carbide semiconductor is used for developing silicon carbide semiconductor elements of various structures such as Schottky barrier diodes, insulated gate field-effect transistors (MOSFET), PN diodes, insulated gate bipolar transistors (IGBTs), and gate turn-off thyristors (GTO).
Multiple photomasks are necessary for producing such semiconductor elements. The photomasks are used in a process of dry etching of silicon carbide, a process of ion implantation into silicon carbide, a process of forming a contact hole of an oxide film, and a process of forming electrode patterns such as a source electrode, a gate electrode, and an emitter electrode. To automatically align the photomasks and a semiconductor substrate in the processes, an alignment mark acting as a position recognition target is first formed on a surface of a silicon carbide substrate. A conventional alignment mark forming process will be described with reference to FIGS. 5 and 6.
FIG. 5 is a cross-sectional view of a state of the silicon carbide substrate during conventional alignment mark formation. FIG. 6 is a cross-sectional view of a state of the silicon carbide substrate after conventional alignment mark formation. First, as depicted in FIG. 5, in a first process of producing an element structure of a silicon carbide semiconductor element, an oxide layer 102 with a sufficiently thick film thickness is formed on a silicon carbide substrate 101 and a photoresist 103 is then applied to a surface of the oxide layer 102. The photoresist 103 is irradiated with (exposed to) ultraviolet light through a photomask provided with an alignment mark.
The photoresist 103 in an exposed portion is removed by immersion in developer. As a result, the photoresist 103 in an unexposed portion remains in the same pattern as the photomask. The remaining photoresist 103 is baked to cure. The remaining photoresist 103 is used as a mask to remove the oxide layer 102 exposed in an opening portion of the photoresist 103 through dry etching using methane trifluoride (CHF3), etc. as the main raw material gas.
As depicted in FIG. 6, the photoresist 103 is entirely removed by ashing. The oxide layer 102 is used as a mask to remove the silicon carbide substrate 101 exposed in an opening portion of the oxide layer 102 to a depth of about 1 to 2 μm through dry etching using fluorine sulfide (SF6), carbon tetrafluoride (CF4), etc. as main raw material gas. As a result, a concave-shaped alignment mark 104 is formed in the silicon carbide substrate 101. Subsequently, the oxide layer 102 is removed through wet etching using buffered hydrofluoric acid (BHF: buffered hydrogen fluoride) etc.
The alignment mark 104 is formed not only in the oxide layer 102 but also in the silicon carbide substrate 101 in this way because the oxide layer 102 must be removed to leave only the silicon carbide substrate 101 for an annealing step executed at a temperature of 1500 degrees C. or higher for the purpose of activation of ion implantation species implanted into the silicon carbide substrate 101. If the annealing step is executed in a state in which the oxide layer 102 is formed on the silicon carbide substrate 101, the oxide layer 102 evaporates due to the high annealing temperature of 1500 degrees C., causing a problem that the silicon carbide substrate 101 is etched when the oxide layer 102 evaporates.
In an example of a fabrication method of a silicon carbide semiconductor element, after an alignment mark is formed in the silicon carbide substrate, an epitaxial layer may be grown on a surface of the silicon carbide semiconductor provided with the alignment mark. For example, a base layer of a MOSFET is generally formed by ion implantation and is known as being formed by epitaxial growth in which crystals are enlarged while atomic arrangement of the crystals is maintained. A method has been proposed for forming a base layer of a MOSFET through epitaxial growth and suppressing crystal defects in the base layer to improve mobility of carriers flowing through an inversion layer (channel) (see Patent Document 1).
The epitaxial layer grown on a principal surface of the silicon carbide substrate 101 will be described. FIG. 7 is a schematic explanatory view of a state of the principal surface of the silicon carbide substrate for epitaxial growth. To grow an epitaxial layer with fewer defects, a <0001> c-axis of the silicon carbide substrate 101 must be tilted slightly from a normal line N direction of a principal surface 110 in a <11-20> direction. FIG. 7 depicts a state in which the axis is tilted from the normal line N direction of the principal surface 110 by α degrees in the <11-20> direction. In this case, since a stepped {0001} c-plane emerges on the principal surface 110 of the silicon carbide substrate 101, the principal surface 110 of the silicon carbide substrate 101 includes a {0001} c-plane terrace portion 111 having a weak interatomic bonding force and a step portion 112 having a strong interatomic bonding force.
A growth mechanism of the epitaxial layer includes a combination of reactions such as adsorption of Si atoms and carbon (C) atoms onto the principal surface of the silicon carbide substrate, surface migration (diffusion) and binding of the adsorbed atoms, and desorption (sublimation) of the adsorbed atoms from the principal surface of the silicon carbide substrate. The probability of occurrence of these reactions varies depending on growth conditions such as a substrate temperature and a pressure of raw material gas and changes a growth rate and a crystal defect density in the epitaxial layer. To grow a high-quality epitaxial layer with a lower crystal defect density, it is proposed that growth conditions must be achieved so as to suppress epitaxial growth in the terrace portion 111 and facilitate epitaxial growth in the step portion 112 (see Non-Patent Literature 1).
The epitaxial growth in the terrace portion 111 is epitaxial growth in the <0001> c-axis direction (vertical direction) around a nucleus formed by an atom adsorbed on the terrace portion 111. In this case, the vertical layering sequence of atoms in a 4H structure of a principal surface of an underlying silicon carbide substrate is not reflected. This generally results in an epitaxial layer including cubic silicon carbide (3C—SiC) formed on the principal surface of the underlying silicon carbide substrate. Since 3C—SiC does not have a sufficiently high material physical property as compared to 4H—SiC, the element performance expected of vertical power device semiconductor elements cannot be realized.
On the other hand, in the epitaxial growth in the step portion 112, the epitaxial growth proceeds in the <11-20> direction (lateral direction) such that the step portion 112 is defined as the origin for each of atomic layers in the {0001} c-plane. Therefore, an epitaxial layer is formed that directly takes over the 4H structure of the principal surface of the underlying silicon carbide substrate. To facilitate the epitaxial growth in the step portion 112, a surface migration length of absorbed atoms on the surface of the step portion 112 must be increased. Therefore, an increased substrate temperature and a reduced gas pressure are mainly implemented during epitaxial growth. Such an epitaxial growth mode will hereinafter be referred to as step-flow growth.    Patent Document 1: Japanese Laid-Open Patent Publication No. 2004-036655    Non-Patent Literature 1: T. Kimoto, et al, “Growth mechanism of 6H—SiC in step-controlled epitaxy”, Journal of Applied Physics, Volume 73, Issue 2, pp. 726-732, January 1993